Optimizing Multipliers for the CPU: A ROM based approach

In a modern day CPU, the multiplier has become an important part of an ALU in terms of both power and performance. Modern day multiplier designs provide some enhancements in power and performance over traditional multiplier designs. However, this enhancement, especially from a power perspective, may prove to be inadequate for a low-power application. Using lookup-based tables for multiplication is an attractive alternative to other modern day multiplier applications in order to greatly reduce the amount of power required. Because so much research has been done on reducing the power usage of Read Only Memories (ROMs), lookupbased tables for multiplication can be implemented with a much lower power than traditional designs. While using lookup tables for multiplication has been researched, most approaches still require tables too large for realistic implementation. Both Vinnakota[1] and Ling[4] introduce approaches to reduce the size of their multiplication tables, but neither approach can be used with modern, 32-bit, multipliers feasibly. To achieve multiplication using smaller tables, we introduce a hybrid approach using Vinnakota's method and the Karatsuba algorithm. This hybrid approach is then compared to some of the modern day multiplier architectures. The comparison will be done assuming standard CMOS technology.